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ordering information eorex em488m 1644vtg 128mb (2m ? 4bank ? 16) synchronous dram features ? fully synchronous to positive clock edge ? single 3.3v ? 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length (b/l) - 1, 2, 4, 8 or full page ? programmable cas latency (c/l) - 2 or 3 ? data mask (dqm) for read / write masking ? programmable wrap sequence C sequential (b/l = 1/2/4/8/full page) C interleave (b/l = 1/2/4/8) ? burst read with single - bit write operation ? all inputs are sampled at the rising edge of the system clock ? auto refresh and self refresh ? 4,096 refresh cycles / 64ms (15.6us) description the em488m 1644vtg is synchronous dynamic random access memory (sdram) organized as 2meg words x 4 banks by 16 bits. all inputs and outputs are synchronized with the posit ive edge of the clock. the 128mb sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs an d outputs voltage levels are compatible with lvttl. em488m 1644vtg is available in tsopii 54pin package. * eorex reserves the right to change products or specification without notice. jan. 2014 www.eorex.com 1/18 part no organization max. freq package grade pb em488m1644vt g - 7f 8m x 16 143mhz @cl3 54pin tsopll commercial free em488m1644vt g - 6f 8m x 16 166mhz @cl3 54pin tsopll commercial free em488m1644vt g - 7fe 8m x 16 143mhz @cl3 54pin tsopll extended free em488m1 644vt g - 6fe 8m x 16 166mhz @cl3 54pin tsopll extended free
eorex pi n assignment em488m 1644vtg 54pin tsop - ii jan. 2014 www.eorex.com 2/18
pin description (simplified) eorex em488m 1644vtg jan. 2014 www.eorex.com 3/18 pin name function 38 clk (system clock) master clock input (active on the positive rising edge) 19 /cs (chip select) select s chip when active 37 cke (clock enable) activates the clk when h and deactivates when l. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. 23~26, 29~34, 22, 35 a0~a11 (address) row ad dress (a0 to a11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. ca (ca0 to ca8) is determined by a0 to a8 level at the read or write command cycle clk rising edge. and this column address becomes burst access start addr ess. a10 defines the pre - charge mode. when a10= high at the pre - charge command cycle, all banks are pre - charged. but when a10= low at the pre - charge command cycle, only the bank that is selected by ba0/ba1 is pre - charged. 20, 21 ba0, ba1 (bank address) se lects which bank is to be active. 18 /ras (row address strobe) latches row addresses on the positive rising edge of the clk with /ras l. enables row access & pre - charge. 17 /cas (column address strobe) latches column addresses on the positive risin g edge of the clk with /cas low. enables column access. 16 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 39, 15 udqm, ldqm (data input/output mask) dqm controls i/o buffers. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 dq0~dq15 (data input/output) dq pins have the same function as i/o pins on a conventional dram. 1,14,27/ 28,41,54 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuit s. 3, 9, 43, 49/ 6, 12, 46, 52 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. 36,40 nc (no connection) this pin is recommended to be left no connection on the device.
note: caution exposing the device to stress above those listed in absolute maximum ratings could capacitance (v cc =3.3v, f=1mhz, t a =25c) recommended dc operati ng conditions (t a = - 0c ~+70c) note: * all voltages referred to v ss . eorex absolute maximum rating em488m 1644vtg cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specif ication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. * v ih (max.) = 4.6v for pulse width Q 10ns acceptable * v il (min.) = - 1.5v for pulse width Q 10ns acceptable jan. 2014 www.eorex.com 4/18 symbol item rating units v in , v out input, output voltage - 0.3 ~ v cc +0.3 v v dd , v ddq power supply voltage - 1 ~ +4.6 v t op operating temperature range commercial 0 ~ +70 c e xtended - 25 ~ +85 t stg storage temperature range - 55 ~ +150 c p d power dissipation 1 w i os short circuit current 50 ma symbol parameter min. typ. max. units v dd power supply voltage 3.0 3.3 3.6 v v ddq power supply voltage (for i/o buffer) 3.0 3.3 3 .6 v v ih input logic high voltage 2.0 v dd +0.3 v v il input logic low voltage - 0.3 0.8 v symbol parameter min. typ. max. units c clk clock capacitance - - 3.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml, dqmu - - 3.5 pf c o input/output capacitance - - 5.5 pf
(v dd , v ddq =3.3v ? 0.3v, v ss =0v) *all voltages referenced to v ss . recommended dc operating conditions (continued) eorex recommended dc operating conditions em488m 1644vtg note 1 : i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i cc4 depends on output loading and cycle rates. specified values are obtained with the o utput open. input signals are changed only one time during t ck (min.) note 3: input signals are changed only one time during t ck (min.) note 4: standard power version. jan. 2014 www.eorex.com 5/18 symbol parameter test conditions max. units - 6 - 7 i cc1 operating current (note 1) burst length=1, t rc t rc (min.), i ol =0ma, one bank active 8 0 75 ma i cc2p precharge standby current in power down mode cke v il (max.), t ck =min 10 10 ma i cc2ps cke v il (max.), t ck = 5 5 ma i cc2n precharge standby current in non - power down mode cke v il (min.), t ck =min, /cs=v ih 3 0 3 0 ma i cc2ns cke v il (min.), t ck = , input signals are stable 2 5 2 5 ma i cc3p active standby current in powe r down mode cke v il (max.), t ck =min 4 banks active 30 30 ma i cc3n active standby current in non - power down mode cke v ih (min.), t ck =min, /cs=v ih (min.) 4 banks active 4 5 4 5 ma i cc4 operating current (burst mode) (note 2) t ck =min 1 0 0 9 0 ma i cc5 aut o refresh current (note 3) t ck =min 1 15 1 0 0 ma i cc6 self refresh current cke 0.2v 5 5 (note 4) ma symbol parameter test conditions min. typ. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v - 10 +10 ua i ol out put leakage current 0 v o v ddq , d out is disabled - 10 +10 ua v oh high level output voltage i o = - 4ma 2.4 v v ol low level output voltage i o =+4ma 0.4 v
eorex block diagram em488m 1644vtg au to/self refresh counter a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 memory array dqm write dqm control data in a10 s/a & i/o gating doi a11 ba0 ba1 col. decoder col. add. buffer data out read dqm control mode register set col. add . counter burst counter timing register clk cke /cs /ras /cas /we dqm jan. 2014 www.eorex.com 6/18
(v dd , v ddq =3.3v ? 0.3v, v ss =0v) (v dd , v ddq =3.3v ? 0.3v, v ss =0v) * all v oltages referenced to v ss . eorex ac operating test conditions em488m 1644vtg ac operating test characteristics note 5: t hz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. jan. 2014 www .eorex.com 7/18 symbol parameter - 6 - 7 units min. max. min. max. t ck clock cycle time cl=3 6 - 7 - ns cl=2 7.5 - 10 - t ac access time form cl k cl=3 - 5.4 - 5.4 ns cl=2 - 5.4 - 6 t ch clk high level width 2.5 - 2.5 - ns t cl clk low level width 2.5 - 2.5 - ns t ckh clock input hold time 1 - 1 - ns t cks clock input setup time 1.5 - 1.5 - ns t oh data - out hold time 2.5 - 2.5 - ns t hz data - ou t high impedance time (note 5) 3 6 3 7 ns t lz data - out low impedance time 1 - 1 - ns t ih input hold time 1 - 1 - ns t is input setup time 1.5 - 1.5 - ns t ds data - in setup time 1.5 - 1.5 - ns t dh data - in hold time 1 - 1 - ns item conditions output ref erence level 1.4v/1.4v output load see diagram as below input signal level 2.4v/0.4v transition time of input signals 1ns input reference level 1.4v
(v dd , v ddq =3.3v ? 0.3v, v ss =0v) * all voltages referenced to v ss . eorex em488m 1644vtg ac operatin g test characteristics (continued) note 6: these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) jan. 2014 www.eorex.com 8/18 symbol parameter - 6 - 7 units min. max. min. max. t rc active to active command period (note 6) 60 - 63 - ns t ras active to precharge command period (note 6) 42 100k 45 100k ns t rp precharge to active command period (note 6) 15 - 15 - ns t rcd active to read/write delay time (note 6) 15 - 15 - ns t rrd active(one) to active(another) command (note 6) 12 - 14 - ns t ccd read/write command to read/write command 1 - 1 - clk t dpl date - in to precharge command 2 - 2 - clk t wr write recovery time for auto precharge 2 - 2 - clk t dqw dqm write mask latency 0 - 0 - clk t dqz dqm data out disable latency - 2 - 2 clk t ref refresh time (4,096 cycles) - 64 - 64 ms t srex self refresh exit time 1 - 1 - clk
eorex em488m 1644vtg recommended power on and initialization the following power on and initialization sequence guarantees the device is precondition ed to each user s specific needs. (like a conventional dram) during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed v dd +0.3v o n any of the input pins or v dd supplies. (clk signal started at same time) after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also re quired, and these may be done before or after programming the mode register. jan. 2014 www.eorex.com 9/18
se lf e ck h wr ite wit pr e se lf ex it e ck act t adbs e r ad re wit h e pr eorex simplified state diagram em488m 1644vtg jan. 2014 www.eorex.com 10/18
address input for mode register set eorex em488m 1644vtg jan. 2014 w ww.eorex.com 11/18 cas latency a6 a5 a4 reserved 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 burst length sequential interleave a2 a1 a0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 reserved reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 full page reserved 1 1 1 ba1 ba0 a11 a10 a9 a8 a7 operation mode 0 0 0 0 0 0 0 burst read with burst write 0 0 0 0 1 0 0 burst read with single write b a1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length burst type a3 interleave 1 sequential 0
burst type (a3) * page length is a function of i/o organization and column addressing ? 16 (ca0 ~ ca8): 1. command truth table h = high level, l = low level, x = high or low level (don't care), v = valid data input eorex em488m 1644vtg full page = 512bits jan. 2014 www.eorex.com 12/18 burst length a2 a1 a0 sequential addressing interleave addressing 2 x x 0 01 01 x x 0 10 10 4 x 0 0 0123 0123 x 0 1 1230 1032 x 1 0 2301 2301 x 1 1 3012 3210 8 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 full page* n n n cn cn+1 cn+2 - command symbol cke /cs /ras /cas /we ba0, ba1 a10 a11, a9~a10 n - 1 n ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre - charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre - charge writa h x l h l l v h v bank activate act h x l l h h v v v pre - charge select bank pre h x l l h l v l x pre - charge all banks pall h x l l h l x h x mode register set mrs h x l l l l l l v
2. dqm truth table h = high level, l = low level, x = high or low level (don't care), v = valid data input 3. cke truth table remark h = high level, l = low level, x = high or low level (don't care) eorex em488m 1644vtg jan. 2014 www.eorex.com 13/18 item command symbol cke /cs /ras /cas /we addr. n - 1 n activating clock suspend mode entry h l x x x x x any clock suspend mode l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit - l h h x x x x l h l h h x x idle power down entry - h l h x x x x l h h x power down power down exit - l h h x x x x l h h l upper byte write enable/output enable bsth h x l read read h x l read with auto pre - charge reada h x l write writ h x l write with auto pre - charge writa h x l bank act ivate act h x l pre - charge select bank pre h x l pre - charge all banks pall h x l mode register set mrs h x l data write/output enable enb h x h data mask/output disable mask h x l command symbol cke /cs n - 1 n
eorex 4. operative command table (note 7 ) remark h = high level, l = low level, x = high or low level (don't care) em488m 1644vtg jan. 2014 www.eorex.com 14/18 current state /cs /r /c /w addr. command action idle h x x x x desl nop or power down (note 8) l h h h x nop or bst nop l h h l ba/ca/a10 read/reada illegal (note 9) l h l x ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self auto refresh or self refresh (note 10) l l l l op - code mrs mode register accessing row active h x x x x desl nop l h h x x nop or bst nop l h l h ba/ca/a10 read/reada begin read: determine ap (note 11) l h l l ba/ca/a10 writ/writa begin write: determine ap (note 11) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall pre - charge (note 12) l l l h x ref/self illegal (note 10) l l l l op - code mrs illegal read h x x x x desl continue burst to end row active l h h h x nop continue burst to end row active l h h l x bst burst stop row active l h l h ba/ca/a10 read/reada terminate burst, new read: determine ap (note 13) l h l l ba/ca/a10 writ/writa terminate burst, start write: determine ap (note 13, 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre - charging (note 10) l l l h x ref/self illegal l l l l op - code mrs illegal write h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst burst stop row active l h l h ba/ca/a10 read/reada terminate burst, start read: determine ap 7, 8 (note 13, 14) l h l l ba/ca/a10 writ/writa terminate burst, new write: determine ap 7 (note 13) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre - charging (note 15) l l l h x ref/self illegal l l l l op - code mrs illegal
4. operative command table (continued) (note 7 ) remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre - charge eorex em488m 1644vtg jan. 2014 www.eorex.com 15/18 current state /cs /r /c /w addr. command action read with ap h x x x x desl continue burst to end pre - charging l h h h x nop continue burst to end pre - charging l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall ille gal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal write with ap h x x x x desl burst to end write recovering with auto pre - charge l h h h x nop continue burst to end ? write recovering with auto pre - charge l h h l x bst illega l l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal pre - charging h x x x x desl nop enter idle after t rp l h h h x nop nop enter idle after t rp l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall nop enter idle after t rp l l l h x ref/self illegal l l l l op - code mrs illegal row activating h x x x x desl nop enter idle after t rcd l h h h x nop nop enter idle after t rcd l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9, 16) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal
4. operative command table (continued) (note 7 ) remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre - charge eorex em488m 1644vtg note 7: all entries assume that cke was active (high level) during the prec eding clock cycle. note 8: if all banks are idle, and cke is inactive (low level), sdram will enter power down mode. all input buffers except cke will be disabled. note 9: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 10: if all banks are idle, and cke is inactive (low level), sdram will enter self refresh mode. all input buffers except cke will be disabled. note 11: illegal if t rcd is not satisfied. note 12: illegal if t ras is not satisfied. note 13: must satisfy burst interrupt condition. note 14: must satisfy bus contention, bus turn around, and/or write recovery requirements. note 15: must mask preceding data which don't satisfy t dpl . note 16: illegal if t r rd is not satisfied. jan. 2014 www.eorex.com 16/18 current state /cs /r /c /w addr. command action write recovering h x x x x desl nop enter row active after t dpl l h h h x nop nop enter row active after t dpl l h h l x bst nop enter row active after t dpl l h l h ba/ca/a10 read/reada start read, determine ap l h l l ba/ca/a10 writ/writa new write, determine ap (note 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal write recovering with ap h x x x x desl nop enter pre - charge after t dpl l h h h x nop nop enter pre - charge after t dpl l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9, 14) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal l l l h x ref/self illegal l l l l op - code mrs ille gal refreshing h x x x x desl nop enter idle after t rc l h h h x nop/bst nop enter idle after t rc l h h l x bst illegal l h l x x read/writ illegal l l h x x act/pre/pall illegal l l l x x ref/self/mrs illegal mode register accessing h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l x x read/writ illegal l l x x x act/pre/pall/ ref/self/mrs illegal
5. command truth table for cke remark: h = high level, l = low level, x = high or low level (don't care) eorex em488m 1644vtg notes 17: self refresh can be entered only from the both banks idle state. power down can be entered only from both banks idle or row active state. notes 18: must be legal command as defined in operative command table jan. 20 14 www.eorex.com 17/18 current state cke /cs /r /c /w addr. action n - 1 n self refresh h x x x x x x invalid, clk(n - 1) would exit self refresh l h h x x x x self refresh recovery l h l h h x x self refresh reco very l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain self refresh self refresh recovery h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x illegal h l l h h x x illegal h l l h l x x illegal h l l l x x x illegal power down h x x x x x x invalid, clk(n - 1) would exit power down l h x x x x x exit power down idle l l x x x x x maintain power down mode both banks idle h h h x x x refer to operat ions in operative command table h h l h x x h h l l h x h h l l l h x refresh h h l l l l op - code refer to operations in operative command table h l h x x x h l l h x x h l l l h x h l l l l h x self refresh (note 17) h l l l l l op - code refer to operations in operative command table l x x x x x x power down (note 17) row active h x x x x x x refer to operations in operative command table l x x x x x x power down (note 17) any state other than listed above h h x x x x r efer to operations in operative command table h l x x x x x begin clock suspend next cycle (note 18) l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend
eorex package description tsopii - 54pin package em488m 1644vtg jan. 2014 www.eorex.com 18/18 dim millimeters inches min. nom. max. min. nom. max. a ? ? 1.20 ? ? 0.047 a1 ? ? 0.15 ? ? 0.006 a2 0.95 1.00 1.05 0.038 0.04 0.042 b 0.30 ? 0.45 0.012 ? 0.018 c 0.10 ? 0.16 0.004 ? 0.01 d 22.13 ? 22.38 0.871 ? 0.881 e 0.80 basic 0.0315 basic e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.395 0.400 0.405 l 0.58 0.60 0.62 0.016 0.024 0.032

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